The present invention relates to a semiconductor device manufacturing method and a semiconductor device.
In recent years, as a method of forming a wiring structure of a semiconductor device, for example, a method described in Japanese Unexamined Patent Application Publication No. 2010-80525 and a method described in Jon Reid and Jian Zhou, “Electrofill Challenges and Directions for Future Device Generations”, Advanced Metallization Conference 2007 Japan/Asia Session, pp. 26-27 are known.
Japanese Unexamined Patent Application Publication No. 2010-80525 describes a method including the steps of forming a Cu seed film over at least a bottom surface and a side wall of a concave portion of a wafer including a concave portion on the surface thereof, forming an Ru film or a TEOS film so that at least a portion of the Cu seed film located over the bottom surface of the concave portion is exposed and the Ru film or the TEOS film covers a portion of the Cu seed film located over the side wall of the concave portion, supplying electric current to the Cu seed film, forming a Cu plating film by an electroplating method so that the Cu plating film is deposited in the concave portion over which the Ru film is formed, performing a heat treatment on the Cu plating film, and then selectively removing the Ru film or the TEOS film. Japanese Unexamined Patent Application Publication No. 2010-80525 describes that the method can prevent the plating from growing from the side wall of the concave portion and reduce generation of voids.
Jon Reid and Jian Zhou, “Electrofill Challenges and Directions for Future Device Generations”, Advanced Metallization Conference 2007 Japan/Asia Session, pp. 26-27 describes a technique for filling a trench of high aspect ratio with Cu by using a film formation accelerator and a macromolecular film formation retardant.